1. Field
Embodiments disclosed herein generally relate to methods for forming a silicon-containing layer. More particularly, embodiments herein relate to methods for forming a silicon-containing layer that may be used in thin film transistor (TFT) devices.
2. Description of the Related Art
Low Temperature Poly Silicon (LTPS) is commonly used as the channel layer in the next generation TFT display and Active Matrix Organic Light Emitting Diode (AMOLED) due to benefits including high mobility (>50 cm2/Vs) and producibility under low temperature (<500° C.). LTPS is commonly produced using an amorphous silicon structure.
A common method to crystallize the amorphous silicon structure in industry is through excimer laser annealing (ELA). Both film properties of the amorphous silicon structure and process conditions of the ELA have effects in determining the process of the crystallization and therefore the film properties as well as the final device performance.
The ever-progressing display technology calls for a channel layer with larger driving current, better uniformity and less production cost. These demands require high quality polycrystalline silicon with higher mobility (above 90 cm2/Vs) while keep using current equipment set of Plasma Enhanced Chemical Vapor Deposition (PECVD) and the ELA tool. Larger and more uniform crystalline grain size can benefit mobility. However, current techniques are limited to a grain size below 300˜500 nm.
Thus, there is a continuing need for methods of forming highly crystalline silicon-containing materials.